1. Field of the Invention
The present invention relates to a semiconductor device including a ferroelectric capacitor configured by interposing a ferroelectric film between a pair of electrodes, and to a method of manufacturing the semiconductor device.
2. Description of the Prior Art
Memories including a ferroelectric capacitor (Ferroelectric Random Access Memories; hereinafter referred to as a “FeRAMs”) for storing information by use of hysteresis characteristics of a ferroelectric have been developed in recent years. FeRAMs are non-volatile memories which can retain information when not powered, and exhibit such advantageous characteristics that the FeRAMs can realize high integration, high-speed read and write operations, high endurance, and low power consumption.
Ferroelectric oxides having a perovskite crystal structure are chiefly used as a material for a ferroelectric film of a ferroelectric capacitor. Ferroelectric oxides include PZT (Pt(Zr, Ti)O3) and SBT (SrBi2Ta2O9), each of which has a larger remnant polarization. The remnant polarizations respectively of these ferroelectric oxides are approximately 10 μC/cm2 to 30 μC/cm2.
In the case of a ferroelectric film made of one of the aforementioned oxides, it has been known that moisture reaching the ferroelectric film from the outside through the interlayer dielectric formed of a silicon dioxide film or the like deteriorates the ferroelectric properties of the ferroelectric film. Specifically, once moisture enters an interlayer dielectric formed of silicon dioxide or the like, the moisture is dissolved into hydrogen and oxygen in a film forming step and in other high-temperature steps. Hydrogen produced by dissolution of the moisture enters the ferroelectric film, and reacts on oxygen contained in the ferroelectric film. Hence, oxygen defects arise, and accordingly crystallizability of the ferroelectric film is reduced. As a result, this deterioration decreases the remnant polarization and the dielectric constant of the ferroelectric film, and accordingly deteriorates performance of the ferroelectric capacitor. In an extreme case, it is likely that the entrance of the moisture and the hydrogen may deteriorate not only the performance of the ferroelectric capacitor but also performance of the transistor and the like. In addition, it has been known that, in a case where a FeRAM is used for a long period of time, hydrogen similarly enters the ferroelectric film so that performance of the ferroelectric capacitor is deteriorated.
For the purpose of avoiding such types of performance deterioration, a conventional practice for semiconductor devices each having a ferroelectric capacitor is to form a barrier layer for preventing hydrogen and moisture from entering the ferroelectric film on top of the ferroelectric capacitor and the interconnection layer. For example, aluminum oxide (Al2O3: alumina) is used for this barrier layer.
Japanese Patent Application No. 2003-100994 (hereinafter referred to as “Patent Document 1”) discloses the following two points. First, a moisture dispersion preventing layer made of SiN (silicon nitride) or SiON (silicon oxynitride) is formed above an interlayer dielectric covering a ferroelectric capacitor. Second, a hydrogen dispersion preventing layer made of tantalum pentoxide (Ta2O3) or alumina is formed on or under the moisture dispersion preventing layer.
Japanese Patent Application No. 2000-164817 (hereinafter referred to as “Patent Document 2”) discloses that, in a case of a ferroelectric memory having a protective film with moisture vapor resistance (a SiN film or a SiO2 film) which is formed on an interlayer dielectric thereof, a protective film made of iridium, alumina or the like is formed between the interlayer dielectric and the protective film with moisture vapor resistance. The type of protective film is used for easing influence on the ferroelectric film of stress generated by contact between the protective film with moisture vapor resistance and the interconnection layer.
Japanese Patent Application No. 2005-191325 (hereinafter referred to as “Patent Document 3”) describes a ferroelectric memory having a moisture dispersion preventing film made of SiN or SiON which is formed on the interlayer dielectric thereof. According to Patent Document 3, an interconnection connected to the transistor is formed on the moisture dispersion preventing film, and this formation prevents moisture from entering the ferroelectric film while the interconnection is being formed.
Japanese Patent Application No. 2006-49795 (hereinafter referred to as “Patent Document 4”) describes a semiconductor device including a first hydrogen dispersion preventing film, an interlayer dielectric and a second hydrogen dispersion preventing film. The first hydrogen dispersion preventing film covers the ferroelectric capacitor. The interlayer dielectric is formed on the hydrogen dispersion preventing film, and its surface is planarized. The second hydrogen dispersion preventing film is formed on the interlayer dielectric. According to Patent Document 4, the first and second hydrogen dispersion films are made of aluminum oxide.
Nevertheless, the present applicants have considered that conventional techniques include the following problems. Specifically, in a case of the conventional techniques, a barrier layer made of aluminum oxide is formed directly on the ferroelectric capacitor, for example. Thus, this barrier layer prevents hydrogen and moisture from entering the ferroelectric film. In this case, a step is inevitably caused in the barrier layer, and a gap allowing hydrogen and moisture to enter the ferroelectric film is prone to be caused in a portion including this step in the barrier layer. This is because aluminum oxide exhibits poor drape. For this reason, this type of conventional technique does not bring about an effect of sufficiently preventing degeneration of performance of the ferroelectric capacitor.
In some cases, the barrier is formed on not only the ferroelectric capacitor but also the interconnection layer. In this case, however, a gap allowing hydrogen and moisture to enter the barrier layer is caused because of a step caused in the interconnection layer. As a result, this type of conventional technique can not fully prevent degeneration of properties of the ferroelectric capacitor.
Furthermore, in the case of a conventional type of FeRAM, it is a usual practice that the ferroelectric capacitor is formed after a W (tungsten) plug to be connected to an impurity region (source/drain of a transistor) in the surface of the semiconductor substrate is formed. In this case, it is likely that the W plug may be oxidized while a step of annealing the ferroelectric film is being performed. This type of conventional technique requires a step of forming an insulating film on the W plug before annealing, and a step of removing the insulating film after annealing. This increases the number of steps to be performed.
According to Patent Document 4, the first barrier layer is formed directly on the ferroelectric capacitor, and additionally the second barrier layer is formed after planarizing the surface of the interlayer dielectric on the first barrier layer. In a case where no second barrier layer is formed, moisture in the interlayer dielectric is discharged to the outside while the ferroelectric film is being annealed. However, in a case where the second barrier layer is formed, the existence of the second barrier layer makes it impossible to discharge the moisture in the interlayer dielectric. This brings about a cause of degeneration of properties of the ferroelectric capacitor.
In addition, according to Patent Document 4, a shallow contact hole and a deep contact hole are formed simultaneously. The shallow contact hole extends from the surface of the interlayer dielectric, and reaches the upper electrode of the ferroelectric capacitor. The deep contact hole extends from the surface of the interlayer dielectric, and reaches the plug in the lower layer. It is likely that, while a step of forming this contact hole is being performed, etching may damage the ferroelectric film, and that, as a result, the properties of the ferroelectric capacitor may be deteriorated.